This invention relates to semiconductor processing methods of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith.
The high speed operation of future higher density integrated circuits will be dictated by interconnect response. Realization of such high speed circuitry is impacted by cross-talk between different adjacent interconnect lines. Cross-talk imposes the biggest constraint on high speed operation when frequencies exceed 500 MHz. Lowering the metal conductor resistivity or the dielectric constant of insulators interposed between metal lines is not expected to inherently solve the cross-talk problem. In addition, the gain in system response is only enhanced by a factor of 3, at best, when these changes are ideally integrated into manufacturing processes.
One proposed method for eliminating cross-talk is in the provision of co-axial interconnect lines, such as described in Thomas et al., VLSI xe2x80x9cMultilevel Micro-Co-Axial Interconnects for High Speed Devicesxe2x80x9d, IEDM 90-55, pp. 3.5.1-3.5.4 (1990). Such technique shields each conductive line in an outer co-axial layer which is the connected to ground or some other suitable potential to overcome or shield cross-talk between adjacent lines.
This disclosure comprises an improvement to such co-axial interconnect lines and methods of forming such.